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SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions.
TM
memory
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50212-3E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
32M (x16) FLASH MEMORY & 16M (x16) SRAM Interface FCRAM
MB84VD22386EJ/VD22387EJ/VD22388EJ-85/90 MB84VD22396EJ/VD22397EJ/VD22398EJ-85/90
s FEATURES
* Power Supply Voltage of 2.7 V to 3.1 V for FCRAM * Power Supply Voltage of 2.7 V to 3.3 V for Flash * High Performance 85 ns maximum access time (Flash) 85 ns maximum access time (FCRAM) * Operating Temperature -30 C to +85 C * Package 71-ball BGA
(Continued)
s PRODUCT LINE-UP
Flash Memory Power Supply Voltage (V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) VCCf* = 2.7 to 3.3 85 85 35 FCRAM VCCs* = 2.7 to 3.1 85 85 50
*: Both VCCf and VCCs must be the same level when either part is being accessed.
s PACKAGE
71-ball plastic BGA
(BGA-71P-M02) Note : These guarantee both FCRAM and Flash at 85 ns Access Cycle.
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
1. FLASH MEMORY
* Simultaneous Read/Write Operations (Dual Bank) Multiple devices available with different bank sizes Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program * Minimum 100,000 Write/Erase Cycles * Sector Erase Architecture Eight 4 K words and sixty three 32 K words. Any combination of sectors can be concurrently erased. The devices also support full chip erase. * Boot Code Sector Architecture MB84VD22386EJ/VD22387EJ/VD22388EJ: Top sector MB84VD22396EJ/VD22397EJ/VD22398EJ: Bottom sector * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion * Ready-Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. * Hidden ROM (Hi-ROM) Region 64 Kbyte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC Input Pin Allows protection of boot sectors at VIL, regardless of sector protection/unprotection status (MB84VD22386EJ/VD22387EJ/VD22388EJ: SA69,SA70 MB84VD22396EJ/VD22397EJ/VD22398EJ: SA0,SA1) Allows removal of boot sector protection at VIH. At VACC, program time will reduce by 40%. * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Please Refer to "MBM29DL32XTE/BE" Data Sheet in Detailed Function
2. FCRAM
* Power Dissipation Operating: 20 mA Max Standby: 70 A Max Power Down: 10 A Max * Power Down Control by CE2s * Byte Write Control: LBs (DQ7-DQ0), UBs (DQ15-DQ5) * 4 Words Address Access Capability
2
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s PIN ASSIGNMENT
(Top View) Marking side
A8 N.C.
B8 N.C.
D8 A15
E8 N.C.
F8 N.C.
G8 A16
H8 Vccf
J8 Vss
L8 N.C.
M8 N.C.
A7 N.C.
B7 N.C.
C7 A11
D7 A12
E7 A13
F7 A14
G7 N.C.
H7 DQ15
J7 DQ7
K7 DQ14
L7 N.C.
M7 N.C.
C6 A8
D6 A19
E6 A9
F6 A10
G6 DQ6
H6 DQ13
J6 DQ12
K6 DQ5
C5 WE
D5 CE2s
E5 A20
H5 DQ4
J5 Vccs
K5 N.C.
C4
D4
E4 RY/BY
H4 DQ3
J4 Vccf
K4 DQ11
WP/ACC RESET
C3 LBs
D3 UBs
E3 A18
F3 A17
G3 DQ1
H3 DQ9
J3 DQ10
K3 DQ2
A2 N.C.
C2 A7
D2 A6
E2 A5
F2 A4
G2 VSS
H2 OE
J2 DQ0
K2 DQ8
L2 N.C.
M2 N.C.
A1 N.C.
B1 N.C.
D1 A3
E1 A2
F1 A1
G1 A0
H1 CEf
J1 CE1s
L1 N.C.
M1 N.C.
(BGA-71P-M02)
3
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s PIN DESCRIPTIONS
Pin Name A19 to A0 A20 DQ15 to DQ0 CEf CE1s CE2s OE WE RY/BY UBs LBs RESET WP/ACC N.C. VSS VCCf VCCs Input/Output I I I/O I I I I I O I I I I -- Power Power Power Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (FCRAM) Chip Enable (FCRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Open Drain Output Upper Byte Control (FCRAM) Lower Byte Control (FCRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (FCRAM) Function
4
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s BLOCK DIAGRAM
VCCf A20 to A0 A20 to A0 WP/ACC RESET CEf 32 M bit Flash Memory DQ15 to DQ0 VSS RY/BY
DQ15 to DQ0 VCCs A19 to A0 DQ15 to DQ0 LBs UBs WE OE CE1s CE2s 16 M bit FCRAM VSS
5
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s DEVICE BUS OPERATION
Operation *1, *2 Full Standby Output Disable *3 Read from Flash *4 Write to Flash Read from FCRAM *5 Write to FCRAM Temporary Sector Group Unprotection *6 Flash Hardware Reset Boot Block Sector Write Protection FCRAM Power Down *8 CEf CE1s CE2s OE WE LBs UBs DQ7 to DQ0 DQ15 to DQ8 RESET H H L L L H H H L H H H L L H H H H H H H X H H L H L H X H H H L H L X X X X X X L H L X X X X X H X X X H X L X X X X X X X X X X X X X X X X X X L L H X X X X High-Z High-Z High-Z DOUT DIN DOUT DIN High-Z DIN X High-Z X X High-Z High-Z High-Z DOUT DIN DOUT DIN DIN High-Z X High-Z X X VID L X X X X L X H X H H H H H WP/ACC *7 X X X X X
Legend: L = VIL, H = VIH, X = VIL or VIH. See "
DC CHARACTERISTICS" for voltage levels.
*1: Other operations except for indicated this column are prohibited. *2: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. *3: FCRAM Output Disable condition should not be kept longer than 1 s. *4: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5: FCRAM Byte control at Read operation is not supported. *6: Also used for the extended sector group protections. *7: Protect "outermost" 2 x 8 Kbytes (4 words) on both ends of the boot block sectors. *8: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
6
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
* Eight 4 K words, and sixty three 32 K words. * Individual-sector, multiple-sector, or bulk-erase capability.
SA70 : 8KB (4KW) SA69 : 8KB (4KW) SA68 : 8KB (4KW) SA67 : 8KB (4KW) SA66 : 8KB (4KW) SA65 : 8KB (4KW) SA64 : 8KB (4KW) SA63 : 8KB (4KW) SA62 : 64KB (32KW) SA61 : 64KB (32KW) SA60 : 64KB (32KW) SA59 : 64KB (32KW) SA58 : 64KB (32KW) SA57 : 64KB (32KW) SA56 : 64KB (32KW) SA55 : 64KB (32KW) SA54 : 64KB (32KW) SA53 : 64KB (32KW) SA52 : 64KB (32KW) SA51 : 64KB (32KW) SA50 : 64KB (32KW) SA49 : 64KB (32KW) SA48 : 64KB (32KW) SA47 : 64KB (32KW) SA46 : 64KB (32KW) SA45 : 64KB (32KW) SA44 : 64KB (32KW) SA43 : 64KB (32KW) SA42 : 64KB (32KW) SA41 : 64KB (32KW) SA40 : 64KB (32KW) SA39 : 64KB (32KW) SA38 : 64KB (32KW) SA37 : 64KB (32KW) SA36 : 64KB (32KW) SA35 : 64KB (32KW) SA34 : 64KB (32KW) SA33 : 64KB (32KW) SA32 : 64KB (32KW) SA31 : 64KB (32KW) SA30 : 64KB (32KW) SA29 : 64KB (32KW) SA28 : 64KB (32KW) SA27 : 64KB (32KW) SA26 : 64KB (32KW) SA25 : 64KB (32KW) SA24 : 64KB (32KW) SA23 : 64KB (32KW) SA22 : 64KB (32KW) SA21 : 64KB (32KW) SA20 : 64KB (32KW) SA19 : 64KB (32KW) SA18 : 64KB (32KW) SA17 : 64KB (32KW) SA16 : 64KB (32KW) SA15 : 64KB (32KW) SA14 : 64KB (32KW) SA13 : 64KB (32KW) SA12 : 64KB (32KW) SA11 : 64KB (32KW) SA10 : 64KB (32KW) SA9 : 64KB (32KW) SA8 : 64KB (32KW) SA7 : 64KB (32KW) SA6 : 64KB (32KW) SA5 : 64KB (32KW) SA4 : 64KB (32KW) SA3 : 64KB (32KW) SA2 : 64KB (32KW) SA1 : 64KB (32KW) SA0 : 64KB (32KW) 1FFFFFh 1FF000h 1FE000h 1FD000h 1FC000h 1FB000h 1FA000h 1F9000h 1F8000h 1F0000h 1E8000h 1E0000h 1D8000h 1D0000h 1C8000h 1C0000h 1B8000h 1B0000h 1A8000h 1A0000h 198000h 190000h 188000h 180000h 178000h 170000h 168000h 160000h 158000h 150000h 148000h 140000h 138000h 130000h 128000h 120000h 118000h 110000h 108000h 100000h 0F8000h 0F0000h 0E8000h 0E0000h 0D8000h 0D0000h 0C8000h 0C0000h 0B8000h 0B0000h 0A8000h 0A0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 000000h
Bank 1
MB84VD22386EJ
Bank 1
MB84VD22387EJ
Bank 1
MB84VD22388EJ
Bank 2
MB84VD22386EJ
Bank 2
MB84VD22387EJ
Bank 2
MB84VD22388EJ
MB84VD22386EJ/VD22387EJ/VD22388EJ Sector Architecture (Top Boot Block)
(Continued)
7
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
1FFFFFh 1F8000h 1F0000h 1E8000h 1E0000h 1D8000h 1D0000h 1C8000h 1C0000h 1B8000h 1B0000h 1A8000h 1A0000h 198000h 190000h 188000h 180000h 178000h 170000h 168000h 160000h 158000h 150000h 148000h 140000h 138000h 130000h 128000h 120000h 118000h 110000h 108000h 100000h 0F8000h 0F0000h 0E8000h 0E0000h 0D8000h 0D0000h 0C8000h 0C0000h 0B8000h 0B0000h 0A8000h 0A0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h
Bank 2
MB84VD22398EJ
Bank 2
MB84VD22397EJ
Bank 2
MB84VD22396EJ
Bank 1
MB84VD22398EJ
Bank 1
MB84VD22397EJ
Bank 1
MB84VD22396EJ
SA70 : 64KB (32KW) SA69 : 64KB (32KW) SA68 : 64KB (32KW) SA67 : 64KB (32KW) SA66 : 64KB (32KW) SA65 : 64KB (32KW) SA64 : 64KB (32KW) SA63 : 64KB (32KW) SA62 : 64KB (32KW) SA61 : 64KB (32KW) SA60 : 64KB (32KW) SA59 : 64KB (32KW) SA58 : 64KB (32KW) SA57 : 64KB (32KW) SA56 : 64KB (32KW) SA55 : 64KB (32KW) SA54 : 64KB (32KW) SA53 : 64KB (32KW) SA52 : 64KB (32KW) SA51 : 64KB (32KW) SA50 : 64KB (32KW) SA49 : 64KB (32KW) SA48 : 64KB (32KW) SA47 : 64KB (32KW) SA46 : 64KB (32KW) SA45 : 64KB (32KW) SA44 : 64KB (32KW) SA43 : 64KB (32KW) SA42 : 64KB (32KW) SA41 : 64KB (32KW) SA40 : 64KB (32KW) SA39 : 64KB (32KW) SA38 : 64KB (32KW) SA37 : 64KB (32KW) SA36 : 64KB (32KW) SA35 : 64KB (32KW) SA34 : 64KB (32KW) SA33 : 64KB (32KW) SA32 : 64KB (32KW) SA31 : 64KB (32KW) SA30 : 64KB (32KW) SA29 : 64KB (32KW) SA28 : 64KB (32KW) SA27 : 64KB (32KW) SA26 : 64KB (32KW) SA25 : 64KB (32KW) SA24 : 64KB (32KW) SA23 : 64KB (32KW) SA22 : 64KB (32KW) SA21 : 64KB (32KW) SA20 : 64KB (32KW) SA19 : 64KB (32KW) SA18 : 64KB (32KW) SA17 : 64KB (32KW) SA16 : 64KB (32KW) SA15 : 64KB (32KW) SA14 : 64KB (32KW) SA13 : 64KB (32KW) SA12 : 64KB (32KW) SA11 : 64KB (32KW) SA10 : 64KB (32KW) SA9 : 64KB (32KW) SA8 : 64KB (32KW) SA7 : 8KB (4KW) SA6 : 8KB (4KW) SA5 : 8KB (4KW) SA4 : 8KB (4KW) SA3 : 8KB (4KW) SA2 : 8KB (4KW) SA1 : 8KB (4KW) SA0 : 8KB (4KW)
MB84VD22396EJ/VD22397EJ/VD22398EJ Sector Architecture (Bottom Boot Block)
8
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22386EJ)
Sector Address Bank Sector Bank Address A20 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 Bank 2 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh (Continued) Address Range
9
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address Bank Sector Bank Address A20 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 Bank 2 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 Bank 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A16 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1F8FFFh 1F9000h to 1F9FFFh 1FA000h to 1FAFFFh 1FB000h to 1FBFFFh 1FC000h to 1FCFFFh 1FD000h to 1FDFFFh 1FE000h to 1FEFFFh 1FF000h to 1FFFFFh Address Range
10
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22396EJ)
Sector Address Sector Bank Address A20 A19 A18 A17 SA0 0 0 0 0 SA1 0 0 0 0 SA2 0 0 0 0 SA3 0 0 0 0 SA4 0 0 0 0 SA5 0 0 0 0 SA6 0 0 0 0 Bank 1 SA7 0 0 0 0 SA8 0 0 0 0 SA9 0 0 0 0 SA10 0 0 0 0 SA11 0 0 0 1 SA12 0 0 0 1 SA13 0 0 0 1 SA14 0 0 0 1 SA15 0 0 1 0 SA16 0 0 1 0 SA17 0 0 1 0 SA18 0 0 1 0 SA19 0 0 1 1 SA20 0 0 1 1 SA21 0 0 1 1 SA22 0 0 1 1 SA23 0 1 0 0 SA24 0 1 0 0 SA25 0 1 0 0 SA26 0 1 0 0 Bank 2 SA27 0 1 0 1 SA28 0 1 0 1 SA29 0 1 0 1 SA30 0 1 0 1 SA31 0 1 1 0 SA32 0 1 1 0 SA33 0 1 1 0 SA34 0 1 1 0 SA35 0 1 1 1 SA36 0 1 1 1 SA37 0 1 1 1 SA38 0 1 1 1 Bank Address Range A16 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh (Continued) 11
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address Sector Bank Address A20 A19 A18 A17 SA39 1 0 0 0 SA40 1 0 0 0 SA41 1 0 0 0 SA42 1 0 0 0 SA43 1 0 0 1 SA44 1 0 0 1 SA45 1 0 0 1 SA46 1 0 0 1 SA47 1 0 1 0 SA48 1 0 1 0 SA49 1 0 1 0 SA50 1 0 1 0 SA51 1 0 1 1 SA52 1 0 1 1 SA53 1 0 1 1 SA54 1 0 1 1 Bank 2 SA55 1 1 0 0 SA56 1 1 0 0 SA57 1 1 0 0 SA58 1 1 0 0 SA59 1 1 0 1 SA60 1 1 0 1 SA61 1 1 0 1 SA62 1 1 0 1 SA63 1 1 1 0 SA64 1 1 1 0 SA65 1 1 1 0 SA66 1 1 1 0 SA67 1 1 1 1 SA68 1 1 1 1 SA69 1 1 1 1 SA70 1 1 1 1 Bank Address Range A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh
12
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22387EJ)
Sector Address Bank Sector Bank Address A20 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 Bank 2 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh (Continued) Address Range
13
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address Bank Sector Bank Address A20 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Bank 2 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 Bank 1 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1F8FFFh 1F9000h to 1F9FFFh 1FA000h to 1FAFFFh 1FB000h to 1FBFFFh 1FC000h to 1FCFFFh 1FD000h to 1FDFFFh 1FE000h to 1FEFFFh 1FF000h to 1FFFFFh Address Range
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22397EJ)
Sector Address Bank Bank Sector Address A20 A19 A18 SA0 0 0 0 SA1 0 0 0 SA2 0 0 0 SA3 0 0 0 SA4 0 0 0 SA5 0 0 0 SA6 0 0 0 SA7 0 0 0 SA8 0 0 0 SA9 0 0 0 SA10 0 0 0 Bank 1 SA11 0 0 0 SA12 0 0 0 SA13 0 0 0 SA14 0 0 0 SA15 0 0 1 SA16 0 0 1 SA17 0 0 1 SA18 0 0 1 SA19 0 0 1 SA20 0 0 1 SA21 0 0 1 SA22 0 0 1 SA23 0 1 0 SA24 0 1 0 SA25 0 1 0 SA26 0 1 0 SA27 0 1 0 SA28 0 1 0 SA29 0 1 0 SA30 0 1 0 Bank 2 SA31 0 1 1 SA32 0 1 1 SA33 0 1 1 SA34 0 1 1 SA35 0 1 1 SA36 0 1 1 SA37 0 1 1 SA38 0 1 1 Address Range A17 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh (Continued) 15
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address Bank Sector Bank Address A20 A19 A18 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address Range A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Bank 2
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh
16
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22388EJ)
Sector Address Bank Sector Bank
Address
Address Range A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh (Continued)
A20 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 Bank 2 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address Bank Sector Bank
Address
Address Range A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Bank 1
SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
A20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1F8FFFh 1F9000h to 1F9FFFh 1FA000h to 1FAFFFh 1FB000h to 1FBFFFh 1FC000h to 1FCFFFh 1FD000h to 1FDFFFh 1FE000h to 1FEFFFh 1FF000h to 1FFFFFh
18
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22398EJ)
Sector Address Bank Sector Bank
Address
Address Range A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Bank 1
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh (Continued) 19
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address Bank Sector Bank
Address
Address Range A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh
A20 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 Bank 2 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
20
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Group Addresses (MB84VD22386EJ/VD22387EJ/VD22388EJ) (Top Boot Block)
Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 A20 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 A17 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 X X X SA60 to SA62 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA31 SA32 to SA35 SA36 to SA39 SA40 to SA43 SA44 to SA47 SA48 to SA51 SA52 to SA55 SA56 to SA59 X X X SA1 to SA3 A14 X A13 X A12 X Sectors SA0
21
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Group Addresses (MB84VD22396EJ/VD22397EJ/VD22398EJ) (Bottom Boot Block)
Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 A17 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X 0 1 0 1 X X X SA70 X X X SA67 to SA69 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 X X X SA8 to SA10 A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
22
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Flash Memory Autoselect Codes
Type Manufacturer's Code MB84VD22386EJ MB84VD22396EJ Device Code MB84VD22387EJ MB84VD22397EJ MB84VD22388EJ MB84VD22398EJ Sector Group protect A19 to A12 BA BA BA BA BA BA BA Sector Group Address A6 VIL VIL VIL VIL VIL VIL VIL VIL A1 VIL VIL VIL VIL VIL VIL VIL VIH A0 VIL VIH VIH VIH VIH VIH VIH VIL Code (HEX) 04h 2255h 2256h 2250h 2253h 225Ch 225Fh 01h *
*: Output 01h at protected sector address and output 00h at unprotected sector address.
23
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Flash Memory Command Definitions
Command Sequence Read/Reset *1 Read/Reset *1 Autoselect Program Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Program Suspend Program Resume Set to Fast Mode Fast Program *2 Reset from Fast Mode *2 Extended Sector Group Protection *3 Query *4 Hi-ROM Entry Hi-ROM Program * Hi-ROM Erase * Hi-ROM Exit *5
5 5
Bus First Bus Second Bus Write Write Cycle Write Cycle Cycles Req'd Addr. Data Addr. Data 1 3 3 4 6 6 1 1 1 1 3 2 2 XXXh 555h 555h 555h 555h 555h BA BA BA BA 555h XXXh BA F0h AAh AAh AAh AAh AAh B0h 30h B0h 30h AAh A0h 90h -- 2AAh 2AAh 2AAh 2AAh 2AAh -- -- -- -- 2AAh PA XXXh -- 55h 55h 55h 55h 55h -- -- -- -- 55h PD F0h*6
Third Bus Write Cycle Addr. -- 555h (BA) 555h 555h 555h 555h -- -- -- -- 555h -- --
Fourth Bus Read/Write Cycle
Fifth Bus Sixth Bus Write Cycle Write Cycle
Data Addr. Data Addr. Data Addr. Data -- F0h 90h A0h 80h 80h -- -- -- -- 20h -- -- -- RA -- PA 555h 555h -- -- -- -- -- -- -- -- RD -- PD AAh AAh -- -- -- -- -- -- -- -- -- -- -- 2AAh 2AAh -- -- -- -- -- -- -- -- -- -- -- 55h 55h -- -- -- -- -- -- -- -- -- -- -- 555h SA -- -- -- -- -- -- -- -- -- -- -- 10h 30h -- -- -- -- -- -- --
4 1 3 4 6 4
XXXh 55h 555h 555h 555h 555h
60h 98h AAh AAh AAh AAh
SPA -- 2AAh 2AAh 2AAh 2AAh
60h -- 55h 55h 55h 55h
SPA -- 555h 555h 555h (HRBA) 555h
40h -- 88h A0h 80h 90h
SPA -- -- PA 555h XXXh
SD -- -- PD AAh 00h
-- -- -- -- 2AAh --
-- -- -- -- 55h --
-- -- -- -- HRA --
-- -- -- -- 30h --
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. *2: This command is valid during Fast Mode. *3: This command is valid while RESET=VID. *4: The valid Address is A6 to A0. *5: This command is valid during Hi-ROM mode. *6: The data "00h" is also acceptable. Notes: Address bits A20 to A11 = X = "H" or "L" for all address commands except for Program Address (PA), Sector Address (SA), and Bank Address (BA). Bus operations are defined in "s DEVICE BUS OPERATION". RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A20 to A15) SPA = Sector group address to be protected. Set sector group address (SPA) and (A6, A1, A0) = (0, 1, 0). 24
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
HRA= Address of the Hidden-ROM area. MB84VD22386EJ/VD22387EJ/VD22388EJ (Top Boot Type) Word mode: 1F8000h to 1FFFFFh Byte mode: 3F0000h to 3FFFFFh MB84VD22396EJ/VD22397EJ/VD22398EJ (Bottom Boot Type) Word mode: 000000h to 007FFFh Byte mode: 000000h to 00FFFFh HRBA = Bank address of the Hidden-ROM area MB84VD22386EJ/VD22387EJ/VD22388EJ (Top Boot Type) A20 = A19 = A18 = A17 = A16 = A15 = 1 MB84VD22396EJ/VD22397EJ/VD22398EJ (Bottom Boot Type) A20 = A19 = A18 = A17 = A16 = A15 = 0 RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected sector addresses. The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0
25
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins *1 VCCf Supply *1 VCCs Supply * RESET *
2 1
Symbol Tstg TA VIN, VOUT VCCf VCCs VIN VIN
Rating Min -55 -30 -0.3 -0.2 -0.2 -0.5 -0.5 Max +125 +85 VCCf +0.3 VCCs +0.3 +3.6 +3.3 +13.0 +10.5
Unit C C V V V V V V
WP/ACC *3
*1: Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCs + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or VCCs + 1.0 V for periods of up to 5 ns. *2: Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +10.5 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature VCCf Supply Voltage VCCs Supply Voltage Symbol TA VCCf VCCs Value Min -30 +2.7 +2.7 Max +85 +3.3 +3.1 Unit C V V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
26
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current ACC Input Leakage Current Flash VCC Active Current (Read) *1 Flash VCC Active Current (Program/Erase) *2 Flash VCC Active Current (Read-While-Program) *5 Flash VCC Active Current (Read-While-Erase) *5 Flash VCC Active Current (Erase-Suspend-Program) FCRAM VCC Active Current
Symbol
Conditions VIN = VSS to VCC VOUT = VSS to VCC VCC = VCC Max, RESET = 12.5 V VCC = VCC Max, WP/ACC = VACC Max CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH VCCs = VCCs Max, tRC / tWC =Min CE1s = VIL, CE2s = VIH, VIN = VIH or VIL, IOUT = 0 mA tRC / tWC =Max VCCf = VCCf Max, CEf = VCCf 0.3 V RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V VCCf = VCCf Max, RESET = VSS 0.3 V, WP/ACC = VCCf 0.3 V VCCf = VCCf Max, CEf = VSS 0.3 V RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V VIN = VCCf 0.3 V or VSS 0.3 V VCCs = VCCs Max,CE1s = CE2s = VIH, VIN = VIH or VIL, IOUT = 0 mA VCCs = VCCs Max,CE1s > VCCs - 0.2 V, CE2s > VCCs- 0.2 V, VIN < 0.2 V or VCCs - 0.2 V, IOUT = 0 mA VCCs = VCCs Max,CE1s > VCCs - 0.2 V, CE2s > VCCs- 0.2 V, VIN Cycle time = tRC Min, IOUT = 0 mA VCCs = VCCs Max, VIN > VCCf - 0.2 V or VIN < 0.2 V CE2s < 0.2 V, IOUT = 0 mA tCYCLE = 5 MHz tCYCLE = 1 MHz
Value Min -1.0 -1.0 -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- 15 2.5 1 Max +1.0 +1.0 35 20 18 7 35 53 53 35 20 3.0 5
Unit A A A mA mA mA mA mA mA mA
ILI ILO ILIT ILIA ICC1f ICC2f ICC3f ICC4f ICC5f
ICC1s
mA
Flash VCC Standby Current Flash VCC Standby Current (RESET) Flash VCC Current (Automatic Sleep Mode) *3
ISB1f
A A
ISB2f
--
1
5
ISB3f
--
1
5
A
FCRAM VCC Standby Current
ISBs
--
0.5
1
mA A
FCRAM VCC Standby Current
ISB1s
--
--
70
FCRAM VCC Standby Current
ISB2s
--
--
5 *6
mA
FCRAM VCC Power Down Current
IPDs
--
--
10
A
(Continued)
27
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Parameter Input Low Level Input High Level Voltage for Autoselect and Sector Protection (RESET) *4 Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration FCRAM Output Low Level FCRAM Output High Level Flash Output Low Level Flash Output High Level Low Vcc Lock-Out Voltage
Symbol
Conditions -- -- -- -- VCCs = VCCs Min, IOL =1.0 mA VCCs = VCCs Min, IOH = -0.5 mA VCCf = VCCf Min, IOL = 4.0 mA VCCf = VCCf Min, IOH = -0.1 mA --
Value Min -0.3 2.3 11.5 8.5 -- 2.1 -- VCCf- 0.4 2.3 Typ -- -- -- 9.0 -- -- -- -- -- Max 0.4
VCC+0.3
Unit V V V V V V V V V
VIL VIH VID VACC VOL VOH VOL VOH VLKO
12.5 9.5 0.4 -- 0.45 -- 2.5
*1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: Applicable for only VCC applying. *5: Embedded Algorithm (program or erase) is in progress. (@5MHz) *6: ISB2s depends on VIN cycle time. Refer to "s APPENDIX".
28
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s AC CHARACTERISTICS
* CE Timing Parameter CE Recover Time CE Hold Time Symbol JEDEC -- -- Standard tCCR tCHOLD Condition -- -- Value Min 0 3 Max -- -- Unit ns ns
* Timing Diagram for alternating FCRAM to Flash
CEf
tCCR
tCCR
CE1s
WE
tCHOLD tCHOLD
tCCR
tCCR
CE2s
29
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* Read Only Operations Characteristics (Flash) Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode Symbol JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- Standard tRC tACC tCE tOE tDF tDF tOH tREADY Conditions -- CEf = VIL OE = VIL OE = VIL -- -- -- -- -- Value Min 85 -- -- -- -- -- 0 -- Max -- 85 85 35 30 30 -- 20 Unit ns ns ns ns ns ns ns s
Note: Test Conditions- Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V or VCC Timing measurement reference level Input: 0.5xVCC Output: 0.5xVCC
30
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* Read Cycle (Flash)
tRC
Address
Address Stable
tACC
CEf
tOE tDF
OE
tOEH
WE
tCE tOH
Outputs
High-Z
Output Valid
High-Z
* Hardware Reset/Read Operation Timing Diagram (Flash)
tRC
Address
tACC
Address Stable
CEf
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
High-Z
Output Valid
31
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* Erase/Program Operations Characteristics (Flash) Parameter Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time to CEf Low During Toggle Bit Polling Address Hold Time (WE to Addr.) Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling Symbol JEDEC tAVAV tAVWL -- tWLAX -- tDVWH tWHDX -- -- -- -- tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 Standard tWC tAS tASO tAH tAHT tDS tDH tOES tOEH tCEPH tOEPH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH2 Min 85 0 15 45 0 35 0 0 0 10 20 20 0 0 0 0 0 0 35 35 30 30 -- -- Value Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 16 1 Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s
CEf High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Word Programming Operation Sector Erase Operation *1
(Continued)
32
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Parameter VCCf Setup Time Voltage Transition Time * Rise Time to VID *2 Rise Time to VACC Recover Time from RY/BY RESET Pulse Width Delay Time from Embedded Output Enable RESET Hold Time Before Read Program/Erase Valid to RY/BY Delay Erase Time-out Time *
3 2
Symbol JEDEC -- -- -- -- -- -- -- -- -- -- -- Standard tVCS tVLHT tVIDR tVACCR tRB tRP tEOE tRH tBUSY tTOW tSPD Min 50 4 500 500 0 500 -- 200 -- 50 --
Value Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 85 -- 90 -- 20
Unit s s ns ns ns ns ns ns ns s s
Erase Suspend Transition Time *4 *1: This does not include the preprogramming time. *2: This timing is for Sector Protection Operation.
*3: The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. A time-out or "tTOW" from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command(s). *4: When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation.
33
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* Write Cycle (WE control) (Flash)
3rd Bus Cycle Address
555h tWC tAS PA tAH
Data Polling
PA tRC
CEf
tCS tCH tCE
OE
tGHWL tWP tWPH tWHWH1 tOE
WE
tDS tDH tDF tOH
Data
A0h
PD
DQ7
DOUT
DOUT
Notes: * PA is an address of the memory location to be programmed. * PD is data to be programmed at the word address. * DQ7 is the output of the data complement written to the device. * DOUT is the data output written to the device. * Figure indicates the last two out of four bus cycle sequence.
34
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CEf
tDS tDH PD DQ7 DOUT
Data
A0h
Notes: * PA is an address of the memory location to be programmed. * PD is data to be programmed at the word address. * DQ7 is the output of the data complement written to the device. * DOUT is the data output written to the device. * Figure indicates the last two out of four bus cycle sequence.
35
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* AC Waveforms Chip/Sector Erase Operations (Flash)
Address
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA*
CEf
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS AAh tDH 55h 80h AAh 55h
30h for Sector Erase 10h
Data
tVCS
VCCf
*: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
36
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
DQ7
Data DQ7 DQ7 = Valid Data
High-Z
tWHWH1 or 2
DQ6 to DQ0
Data tBUSY
DQ6 to DQ0 = Output Flag tEOE
DQ6 to DQ0 Valid Data
High-Z
RY/BY
* : DQ7 = Valid Data (the device has completed the Embedded operation).
37
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT
tASO
tAHT
tAS
CEf
tCEPH
WE
tOEH tOEPH tOEH
OE
tDH tOE Toggle Data Toggle Data tCE
*
Stop Toggling Output Valid
DQ6/DQ2
Data
tBUSY
Toggle Data
RY/BY
* : DQ6 stops toggling (the device has completed the Embedded operation).
38
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* Back-to-back Read/Write Timing Diagram (Flash)
Read
tRC Address
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
BA1
tAS
BA2 (555h)
tAH tACC
BA1
BA2 (PA)
BA1
tAS tAHT
BA2 (PA)
tCE
CEf
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS tDH tDF
DQ
Valid Output
Valid Input (A0h)
Valid Output
Valid Input (PD)
Valid Output
Status
Note: This is an example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1. BA2: Address of Bank 2.
39
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
WE
RESET
tRP tRB
RY/BY
tREADY
40
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* Temporary Sector Group Unprotection (Flash)
VCCf tVCS VID VIH RESET
tVIDR tVLHT
CEf
WE tVLHT RY/BY Unprotection period Program or Erase Command Sequence tVLHT
* Acceleration Mode Timing Diagram (Flash)
VCCf tVCS VID VIH WP/ACC
tVACCR tVLHT
CEf
WE tVLHT
tVLHT RY/BY Acceleration Mode Period
41
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET tVIDR Address
tVLHT tWC tWC SPAX SPAX SPAY
A0
A1
CEf
OE tWP TIME-OUT
WE
Data
60h
60h
40h tOE
01h
60h
SPAX: Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min)
42
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* READ OPERATION (FCRAM) Parameter Read Cycle Time Chip Enable Access Time Output Enable Access Time Chip Enable Access Time Output Data Hold Time CE1s Low to Output Low-Z OE Low to Output Low-Z CE1s High to Output High-Z OE High to Output High-Z Address Setup Time to CE1s Low Address Setup Time to OE Address Invalid Time CE1s Low to Address Hold Time OE Low to Address Hold Time CE1s High to Address Hold Time OE High to Address Hold Time CE1s Low to OE Low Delay Time OE Low to CE1s High Delay Time CE1s High Pulse Width OE High Pulse Width *1: The output load is 30 pF. *2: The output load is 5 pF. *3: The tCE is applicable if OE is brought to Low before CE1s goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4: Applicable only to A0 and A1 when both CE1s and OE are kept at Low for the address access. *5: Applicable if OE is brought to Low before CE1s goes Low. *6: The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control access (i.e., CE1s stays Low) , the tOE becomes tOE (Max) + tASO (Min) - tASO (actual) . *7: The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access. *8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) - tCLOL (actual) or tRC (Min) - tOP (actual) . *9: Maximum value is applicable if CE1s is kept at Low. 43 Symbol tRC tCE tOE tAA tOH tCLZ tOLZ tCHZ tOHZ tASC tASO tASO[ABS] tAX tCLAH tOLAH tCHAH tOHAH tCLOL tOLCH tCP tOP tOP[ABS] Value Min 90 5 5 0 -5 45 10 90 45 -5 -5 45 45 20 45 20 Max 85 45 85 30 25 5 1000 1000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *6, *8, *9 *7 *4, *6, *8, *9 *8 *1, *3 *1 *1, *4 *1 *2 *2 *2 *2 *5 *3, *6 *7 *4 *4 *4, *8 Notes
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* WRITE OPERATION (FCRAM) Parameter Write Cycle Time Address Setup Time Address Hold Time CE1s Write Setup Time CE1s Write Hold Time WE Setup Time WE Hold Time LBs and UBs Setup Time LBs and UBs Hold Time OE Setup Time OE Hold Time OE High to CE1s Low Setup Time OE High to Address Hold Time CE1s Write Pulse Width WE Write Pulse Width CE1s Write Recovery Time WE Write Recovery Time Data Setup Time Data Hold Time CE1s High Pulse Width Symbol tWC tAS tAH tCS tCH tWS tWH tBS tBH tOES tOEH tOEH[ABS] tOHCL tOHAH tCW tWP tWRC tWR tDS tDH tCP Value Min 90 0 45 0 0 0 0 0 -5 0 45 20 -3 -5 60 60 15 15 20 0 20 Max 1000 1000 1000 1000 1000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *9 *3 *3, *4 *5 *6 *7 *1, *8 *1, *8 *1, *9 *1, *3, *9 Notes *1 *2 *2
*1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) . *2: New write address is valid from either CE1s or WE that is brought to High. *3: Maximum value is applicable if CE1s is kept at Low and both WE and OE are kept at High. *4: The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1s stays Low. *6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1s Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. *7: Applicable if CE1s stays Low after read operation. *8: tCW and tWP are applicable if write operation is initiated by CE1s and WE, respectively. *9: tWRC and tWR are applicable if write operation is terminated by CE1s and WE, respectively. The tWR (Min) can be ignored if CE1s is brought to High together or after WE is brought to High. In such a case, the tCP (Min) must be satisfied.
44
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* POWER DOWN PARAMETER (FCRAM) Parameter CE2s Low Setup Time for Power Down Entry CE2s Low Hold Time after Power Down Entry CE1s High Hold Time following CE2s High after Power Down Exit CE1s High Setup Time following CE2s High after Power Down Exit * OTHER TIMING PARAMETER (FCRAM) Parameter CE1s High to OE Invalid Time for Standby Entry CE1s High to WE Invalid Time for Standby Entry CE2s Low Hold Time after Power-up CE2s High Hold Time after Power-up CE1s High Hold Time following CE2s High after Power-up Input Transition Time Symbol tCHOX tCHWX tC2LH tC2HL tCHH tT Value Min 20 20 50 50 350 1 Max 25 Unit ns ns s s s ns *1 *2 *3 *2 *4 Note Symbol tCSP tC2LP tCHH tCHS Value Min 10 100 350 10 Max Unit ns ns s ns Note
*1: It may write date into any address location tCHWX is not satisfied. *2: Must satisfy tCHH (Min) after tC2LH (Min) . *3: Requires Power Down mode entry and exit after tC2HL. *4: The Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns, it may violate AC specification of some timing parameters. * AC TEST CONDITIONS (FCRAM) Parameter Input High Level Input Low Level Input Timing Measurement Level Input Transition Time
Symbol VIH VIL VREF tT
Condition VCCs = 2.7 V to 3.1 V VCCs = 2.7 V to 3.1 V VCCs = 2.7 V to 3.1 V Between VIL and VIH
Value 2.3 0.4 1.3 5
Unit V V V ns
Note
45
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* READ Timing #1 (OE Control Access) (FCRAM)
tRC
tRC Address Valid tASO tOHAH tOHAH
Address
Address Valid tCE
CE1s
tOLCH tCLOL tCE tOP tOE
OE
tASO tOLZ tOHZ tOH tOLZ tOHZ tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
* READ Timing #2 (CE1s Control Access) (FCRAM)
tRC tRC Address Valid tCHAH tASC tCE tCHAH
Address
tASC
Address Valid tCE
CE1s
tOLCH tOE tCHZ tCP tCHZ
OE
tCLZ tOH tCLZ tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
46
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* READ Timing #3 (Address Access after OE Control Access) (FCRAM)
tRC tRC Address Valid (No change)
Address (A19 - A2)
Address Valid
Address (A1, A0)
tASO
Address Valid tOLAH tAX
Address Valid tAA tOHAH
CE1s
tOE tOHZ
OE
tOLZ tOH tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
* READ Timing #4 (Address Access after CE1s Control Access) (FCRAM)
tRC tRC Address Valid (No change)
Address (A19 - A2)
Address Valid
Address (A1, A0)
tASC
Address Valid tCLAH tAX
Address Valid tAA tCHAH
CE1s
tCE tCHZ
OE
tCLZ tOH tOH
DQ (Output)
Valid Data Output Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
47
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* WRITE Timing #1 (CE1s Control) (FCRAM)
tWC
Address
tAS
Address Valid tAH tAS
CE1s
tCW tWS tWH tWRC tWS
WE
tBS
tBH
tBS
UBs, LBs
tOHCL
OE
tDS tDH
DQ (Input)
Valid Data Input
Note : CE2s must be High during the write cycle.
48
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* WRITE Timing #2-1 (WE Control, Single Write Operetion) (FCRAM)
tWC
Address
tOHAH tAS
Address Valid tAH tCH tAS
CE1s
tCP tOHCL tCS tWP tWR
WE
tBS
tBH
UBs, LBs
tOES
OE
tOHZ tDS tDH
DQ (Input)
Valid Data Input
Note : CE2s must be High during the write cycle.
49
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* WRITE Timing #2 (WE Control, Continuous Write Operetion) (FCRAM)
tWC
Address
tOHAH tAS
Address Valid
tAH tAS
CE1s
tOHCL tCS tWP tWR
WE
tBS tBH tBS
UBs, LBs
tOES
OE
tOHZ tDS tDH
DQ (Input) Valid Data Input
Note : CE2s must be High during the write cycle.
50
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* READ/WRITE Timing #1-1 (CE1s Control) (FCRAM)
tWC
Address
tCHAH tAS
Write Address tAH tASC
Read Address
CE1s
tCP tWH tWS tCW tWH tWRC tWS
WE
tBS tBH
UBs, LBs
tOHCL tCLOL
OE
tCHZ tOH tDS tDH tOLZ tCLZ
DQ
Read Data Output Write Data Input
Note : Write address is vaild from either CE1s or WE of the last falling edge.
51
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* READ/WRITE Timing #1-2 (CE1s Control) (FCRAM)
tRC
Address
tASC tWRC
Read Address tCHAH tAS
Write Address
CE1s
tWRC (Min) tWH tWS tWH tCP tWS
WE
tBH tCE tBS
UBs, LBs
tOEH tOHCL
OE
tCHZ tDH tCLZ tOH
DQ
Write Data Input Read Data Output
Note : tOEH is specified from the time satisfied both tWRC and tWR (Min) .
52
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* READ (OE Control) /WRITE (WE Control) Timing #2-1 (FCRAM)
tWC
Address
tOHAH tAS
Write Address tAH tASO
Read Address
CE1s
Low tWP tWR
WE
tBS tBH
UBs, LBs
tOES tOEH
OE
tOHZ tOH tDS tDH tOLZ
DQ
Read Data Output Write Data Input
Note : CE1s can be tied to Low for WE and OE controlled operation. When CE1s is tied to Low, output is exclusively controlled by OE.
53
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* READ (OE Control) / WRITE (WE Control) Timing #2-2
tRC
Address
tASO
Read Address Valid tOHAH tAS
Write Address
CE1s
Low tWR
WE
tBH tBS
UBs, LBs
tOEH tOE tOES
OE
tOHZ tDH tOLZ tOH
DQ
Write Data Input Read Data Output
Note : CE1s can be tied to Low for WE and OE controlled operation. When CE1s is tied to Low, output is exclusively controlled by OE.
54
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* POWER DOWN Timing (FCRAM)
CE1s
tCHS
CE2s
tCSP tC2LP High-Z tCHH
DQ
Power Down Entry
Power Down Mode
Power Down Exit
* Standby Entry Timing after Read or Write (FCRAM)
CE1s
tCHOX tCHWX
OE
WE
Active (Read) Standby Active (Write) Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period from either last address transition of A0 and A1, or CE1s Low to High transition.
55
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* POWER-UP Timing 1 (FCRAM)
CE1s
tCHS tC2LH tCHH
CE2s
*
VCCs
0V
VCCs Min
* : It is recommended to keep CE2s at Low during VCCs power-up. tC2LH specifies after VCCs reaches specified minimum level.
* POWER-UP Timing 2 (FCRAM)
CE1s
tC2HL tCSP tCHS tC2LP tCHH
CE2s
tC2HL
VCCs
0V
VCCs Min
Note : tC2LH specifies from CE2S Low to High transition after VCCS reaches specified minimum level. CE1s must be brought to High prior to or together with CE2s Low to High transition.
56
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s ERASE AND PROGRAMMING PERFORMANCE (Flash)
Parameter Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle Value Min -- -- -- 100,000 Typ 1 16 -- -- Max 10 360 200 -- Unit s s s cycle Remarks Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead
s DATA RETENTION CHARACTERISTICS (FCRAM)
Parameter VCCS Data Retention Supply Voltage Symbol VDR Conditions CE1s = CE2s VCCs - 0.2 V or, CE1s = CE2s = VIH 2.3 V VCCs 2.7 V, VIN = VIH * or VIL CE1s = CE2s = VIH * , IOUT=0 mA 2.3 V VCCs 2.7 V, VIN 0.2 V or VIN VCCs - 0.2 V, CE1s = CE2s VCCs - 0.2 V, IOUT=0 mA 2.7 V VCCs 3.1 V at data retention entry 2.7 V VCCs 3.1 V after data retention -- Value Min 2.3 Typ -- Max 3.1 Unit V
IDR VCCS Data Retention Supply Current IDR1
--
0.5
1
mA
--
--
70
A
Data Retention Setup Time Data Retention Recovery Time VCCS Voltage Transition Time *: 2.0 V VIH VCCs + 0.3 V
tDRS tDRR V/t
0 90 0.5
-- -- --
-- -- --
ns ns V/s
57
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
* Data Retention Timing
tDRS tDRR
3.1 V
VCCs V/t V/t
2.7 V
CE2s
2.3 V
CE1s VCCs 0.2 V or VIH (*) Min
0.4 V VSS
Data Retention Mode Data bus must be in High-Z at data retention entry.
* : 2.0 V VIH VCCS + 3 V
s PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Condition VIN = 0 V VOUT = 0 V VIN = 0 V VIN = 0 V Value Typ 11 12 14 21.5 Max 14 16 16 26 Unit pF pF pF pF
Note: Test conditions TA = +25C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please handle this package carefully since the sides of package are created acute angles.
s CAUTION
* The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector protect function are used. Then the high voltage (VID) can be applied to RESET. * Without the high voltage (VID) , sector protection can be achieved by using "Extended Sector Group Protection" command.
58
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s ORDERING INFORMATION
MB84VD2238 X EJ -90 -PBS
PACKAGE TYPE PBS = 71-ball BGA SPEED OPTION See Product Selector Guide Device Revision
Bank Size 6 = 4 Mbit / 7 = 8 Mbit / 8 = 16 Mbit /
28 Mbit 24 Mbit 16 Mbit
DEVICE NUMBER/DESCRIPTION 32 Mega-bit (2 M x 16-bit) Dual Operation Flash Memory 3 V-only Read, Program, and Erase 16 Mega-bit(1M x 16-bit) FCRAM BOOT CODE SECTOR ARCHITECTURE 84VD2238 = Top sector 84VD2239 = Bottom sector
59
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s APPENDIX
* ISB2s vs. VIN Cycle time
2.5
2.0
: RT = + 25 C : LT = - 30 C : HT = + 85 C
ISB2s (mA)
1.5
1.0
0.5
0.0
0
200
400
600 VIN cycle time (ns)
800
1000
60
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
s PACKAGE DIMENSION
71-pin plastic FBGA (BGA-71P-M02)
8.80(.346) 11.000.10(.433.004) 1.05 0.10 .041 -.004
+.006 +0.15
(Mounting height)
7.20(.283) 5.60(.220)REF 0.80 (.031) 8 7 6 5 4 3 2 1 MLKJHGFEDCBA
0.380.10 (Stand off) (.015.004)
7.000.10 (.276.004)
5.60(.220) REF 0.80 (.031)
INDEX-MARK AREA 71-O0.45 -0.05 71-O.018 -.002
+0.10 +.004
0.08(.003)
M
0.10(.004)
C
2000 FUJITSU LIMITED B71002S-1c-1
Dimensions in mm (inches).
61
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0111 (c) FUJITSU LIMITED Printed in Japan

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